This application claims the priority of Korean Patent Application No. 2003-35904, filed on Jun. 4, 2003, in the Korean Intellectual Property Office, the contents of which are incorporated herein in their entirety by reference.
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit comprising a unit which detects soft defects in a static memory cell, a method of detecting soft defects, and a method of testing the semiconductor integrated circuit for soft defects.
2. Description of the Related Art
Many complementary metal oxide semiconductor (CMOS) static random access memories (SRAMs) utilize four transistors per memory cell. However, due to some advantages, a six transistor cell approach is, gaining in popularity. These advantages include higher operational stability, higher alpha-particle immunity, and a simpler process.
A primary disadvantage of the six transistor memory cell CMOS SRAM is that open circuit failures in a pull-up circuit of the memory cell can appear as soft defects. Because such faults do not result in a hard failure, testing and failure analysis have proven to be particularly difficult. A method of testing a CMOS SRAM device for soft defects in a pull-up circuit is disclosed in U.S. Pat. No. 5,361,232.
FIG. 1 is a schematic diagram of a modeling circuit of a conventional six transistor static memory cell. FIG. 2 is a schematic diagram of a semiconductor integrated circuit including a plurality of static memory cells shown in FIG. 1.
Referring to FIG. 1, in the six transistor static memory cell, resistors R1, R2 and R3 are located between a power voltage VDD and pull-up transistors MP1 and MP2, and resistors R4 and R5 are located between the pull-up transistors MP1 and MP2 and internal nodes D and DB. Resistors R8, R9 and R10 are located between a ground voltage VSS and pull-down transistors MN3 and MN4, and resistors R6 and R7 are located between the pull-down transistors MN3 and MN4 and the internal nodes D and DB. Typically, the pull-up transistors MP1 and MP2 act as load transistors and the pull-down transistors MN3 and MN4 act as drive transistors.
Referring to the circuit diagram of FIG. 2, during a read operation, when a precharge signal PCH is initially at a logic “L”, PMOS transistors 211, 213, and 215 within a precharge circuit 21 are turned on and a bit line BIT and a complementary bit line BITB are precharged to a power voltage VDD.
Next, when the precharge signal PCH is at a logic “H” and accordingly, the PMOS transistors 211, 213, 215 within the precharge circuit 21 are turned off and one of word lines WL1 through WLn is activated to a logic “H”, one of memory cells M1 through Mn is selected and data D and complementary data DB stored in the selected memory cell are output to the bit line BIT and the complementary bit line BITB, respectively.
After a suitable time delay, a sense enable signal SAEN is activated to a logic “H”, and a sensor amplifier 23 senses and amplifies a voltage difference between the bit line BIT and the complementary bit line BITB and outputs the result as output data.
If soft defects exist in the pull-up circuits of the memory cell, that is, if leakage current continuously flows to a node having data “1”, for example, the node DB, or if the resistances of the resistors R1 through R5 increase for some reason and thus a sufficient amount of current is not applied to the node DB having data “1”, the node DB gradually discharges. That is to say, the voltage level of the node DB gradually decreases. As a result, when the voltage of the node DB exceeds a logic threshold voltage of an inverter within the memory cell, data stored in the memory cell are toggled.
For the purpose of screening memory cells having such soft defects, a retention test is typically run. However, the time taken to discharge the node DB is so long that the retention test time needs to be of very long duration in order to detect the defects.